Semiconductor device fabrication



Feb. 8, 1966 J. c. MARINACE 3,234,440

SEMICONDUCTOR DEVICE FABRICATION I Original Filed Dec. 30, 1959 STEP 4STEP 3 l E 1 STEP 4A '6 T 3 6 W W Q M /+W-';1

STEP 4B 1 i H l H STEP 5A STEP-5B HA HA Fisk?! Es 5 12 12 m e k INVENTORJOHN c. MARINACE ATTORNEY United States Patent 3,234,440 SEMICONDUCTORDEVICE FABRHCATION John C. Marinace, Yorhtown Heights, N.Y., assignor toInternational Business Machines (Iorporation, New York, N.Y., acorporation of New York Original application Dec. 30, 195?, Ser. No.863,000, now Patent No. 3,133,336, dated May 19, 1964. Divided and thisapplication Aug. 14, 1962, Ser. No. 221,648 4 Claims. (Cl. 317234) Thisapplication is a division of application Serial No. 863,000, now PatentNo. 3,133,336, filed Dec. 30, 1959.

This invention relates to the fabrication of semiconductor devices andin particular to the fabrication of a plurality of semi-conductordevices in a single operation.

In the semiconductor art, problems have been encountered in thefabrication of a large number of semiconductor devices by the fact thatthe small physical size of the device results in handling problems incutting to size, in properly orienting the device for the attachment ofelectrodes and in positioning for service. Further, additional problemshave been encountered where the devices are made in a plurality ofseparate fabrication operations so that the same process steps are notapplied to each one and hence the output characteristics of the deviceare different. Under these conditions it is frequently necessary toperform very detailed measurements in order to match up characteristicsso that identical performance may be realized from all similar devicesin an individual circuit.

What has been discovered is a technique of simultaneously fabricating aplurality of semiconductor devices in a single processing operationwherein all devices are simultaneously made in spatial relationship inthe same process steps so that each device will exhibit identicalperformance charcteristics and that as a part of the process, a fixtureemployed in the manufacture is later useable for the purpose ofretaining the devices so made for further fabrication into a matrix.

It is an object of this invention to provide an improved technique offabricating an array of semiconductor devices.

It is another object of this invention to provide a fixture for thefabrication and retention of a plurality of semiconductor devices.

It is another object of this invention to provide a method of depositingan array of semiconductor devices.

It is another object of this invention to provide an improved method ofhandling the small physical sizes of semiconductor devices.

It is another object of this invention to provide a method of forming adiode matrix.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention as illustrated inthe accompanying drawings.

In the drawings:

FIG. 1 is a flow chart of the germanium semiconductor device fabricationprocess in accordance with the invention.

FIG. 2 is a view of a matrix employed in the fabrication ofsemiconductor devices.

FIG. 3 is a complete matrix of fabricated semiconductor devices.

It has been discovered that the use of an apertured glass plate inconnection with an epitaxial germanium vapor deposition process permitsthe simultaneous deposition of a plurality of devices on a germaniumsubstrate. The glass matrix may be used more than once or in thealternative the glass matrix has been found to be of great advantage inretaining the extremely small sizes of the semiconductor devices made.The matrix is fabricated from a thin plate of glass or a materialsimilar to glass which has the following properties. It has lowelectrical conductivity and low chemical activity. The material issufiiciently refractory to withstand the temperatures involved in thedeposition. It is sufiiciently strong to'support a matrix of devices andit has a coefiicient of expansion that is close to that of thesemiconductor material used. It has beenfound that the material glasshas a temperature coefiicient of expansion compatible with that ofgermanium, so that the use of this material with germanium isparticularly advantageous.

Referring now to FIG. 1, a flow chart is shown in a process involvingthe invention wherein in a first step a substrate 1 for example ofgermanium semiconductor material is monocrystalline form is provided.The substrate material has a major surface 2 upon which the depositionis to take place. The substrate 1 is generally previously formed throughthe conventional technique of monocrystalline growing by pulling thecrystal from a melt in a manner well known in the art. The singlecrystal is then sliced longitudinally to provide a relatively largesurface'2 for the deposition.

In step 2, and in FIG. 2, a fixture 3 meeting the above describedcriteria, for example glass is placed in contact with the substrate 1 onthe surface 2. The glass fixture 3 is shown wherein portions 4 of theplate have been subected to a cutting operation such as grinding, sandblastmg, ultrasonic cutting or acid etching to produce any desired arrayof holes or slots through the fixture exposing the surface 2. The slots4 or holes go clear through the plate from one side to the other, andthe walls of the holes or slots may be provided with sufficientinterlocking shape to permit devices deposited in the holes in a laterstep to be retained therein. This may be done either by leavmg the wallsof the holes rough or by shaping them such that the deposited materialis retained. Where it is desued to leave the deposited material attachedto the substrate 1, the walls of the holes 4 may be made smooth for easyremoval of the matrix 3. V

Returning to FIG. 1, step 2, the surface 2 is preferably first etched byreversing the deposition reaction and removing some of the material fromthis surface of the substrate. This exposes a clean surface on which thedeposition is to takeplace In step 3, germanium material is depositedfrom a gas 5 and grows epitaxially on the substrate 1 from theinterface- 2 in the form of elements 6 within the holes. The gas 5 inconnection with the deposition process is a halide vapor, usuallygermanium di-iodide (Gel which is decomposed or disproportionates in thevicinity of the substrate 1 such that free germanium and germaniumtetra, iodide (Gel are formed. The free germanium deposits with the sameperiodicity of crystal structure as that of the originalsubstrate 1. Themethod of vapor deposition has beenestablished in the art and twotechniques of its practice are described in US. Patent No. 3,020,132 andcopending applipation Ser. No. 815,956, filed May 26, 1959, now PatentNo. 3,089,788, both of which are as: signed to the .assignee of thisapplication.

The introduction of conduetivity type determining impurities is undercomplete control in this type of process and any quantity in anygradation and concentration may be introduced into the devices6. WherePN junctions are formed in the devices 6, the PN junction may be formedeither at the interface 2 or within the actual body of element 6 bychanging the concentration of the GQH= ductivity type determiningimpurity present in the gas 5. It has been found that the semiconductormaterial does not deposit to any appreciable degree on the fixture 3 and,what little does deposit may easily be removed by lapping.

As an illustration of the deposition of diodes, a PN junction 7 is shownin the device 6 made by a multiple step deposition process wherein afirst deposition step N conductivity type determining impurities areintroduced into the semiconductor material in the first region 8extending epitaxially from the surface 2 and thereafter P conductivitytype determining impurities are introduced into the elements 6 in asecond region 9. This forms a PN junction between the two regions and isuseable as a diode.

The partial product produced in step 3 may now be fabricated into asemiconductor devices in one of two directions either by using thefixture 3 to retain the deposited elements or by removing the fixture 3leaving the deposited devices retained on the substrate.

Considering first step 4A, wherein the fixture 3 is re-v moved and theindividual semiconductor devices 6 are retained on a substrate 1 in theform of 'a plurality of diodes. The diodes 6 by virtue of beingmonocrystalline extensions of the substrate 1 all have one electrodethereof connected to a common point so that they may then receive asingle plated connection to the substrate 1. Withthis type of structurethe substrate 1 serves as a supporting element to maintain all of theplurality of semiconductor devices 6 that have been fabricated in asingle structure. The structure shown in step 4A, is then provided instep A with electrical connections 10 and 11 such as by soldering orother techniques Well known in the art to provide a completed matrixwherein an individual ohmic, contact 10 is provided to the entiresurface of the substrate 1, and individual contacts 11 which are shownattached to the P region of each of the diodes 6.

The fabrication of matrices of semiconductor devices employingthefixture 3 to retain the devices, in accordance with the invention isaccomplished in connection with steps 43 and 5B. In these steps thematrix 3 may be separated from the substrate 1 through an etching orabrading operation after the deposition whereby the elements 6 arepermitted to remain imbedded in the matrix and the matrix itself servesas a fixture to retain the plurality of semiconductor elements in theproper relationship, When it is desired to employ the fixture 3 toretain the devices, the sides of the holes 4 are usually so constructedas to grip the devices. This feature has been shown in steps 4B and 5Bin the Walls of the holes 4 are equipped with a device retaining feature12 shown by the fact that the hole is larger in the central portion ofthe fixture 3 than at the edge.

In step 5B, the fixture 3 containing the deposited devices 6 is equippedwith ohmic connections to provide a useful circuit component. Forexample, the connections may be a solid ohmic contact 10A joining thesame electrode of all diodes within the fixture 3 and on the oppositeside of the fixture 3 a plurality of individual conductors 11A are madeemploying standard printed wiring techniques, such as plating, known inthe art, to the individual diodes. Such structure is shown in FIG. 3wherein a complete matrix of semiconductor devices is illustratedwherein each of the devices 6 was formed in and is retained in use bythe glass matrix 3. In FIG. 3, as an illustration, the common ohmiccontact 10 is plated on the back of the matrix 3 joining one electrodeof all devices 6 and individual contacts 11A are plated in the oppositesurface of the glass connecting the remaining electrode on the devices6.

What has been described is a technique of simulta neously fabricatingcomplete matrices of semiconductor devices in spatial relationship toeach other through the technique of vapor deposition employing afabrication fixture which may serve to establish the spatialrelationship of the devices and to act as a retaining member forindividual discrete semiconductor devices in service.

While the invention has been particularly shown and described withreference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and details may be madetherein without departing from the spirit and scope of the invention.

What is claimed is:

1. A semiconductor device matrix comprising a mono crystallinesemiconductor element having at least one major surface; adevice-defining insulating mask in contact with said at least one majorsurface; at least two semiconductor devices comprising semiconductormaterial, formed within said apertures in said device-defining maskspatially separated on said major surface, in contact with said elementto define semiconductor junctions respectively Within said aperturesabove the surface of said element: and at least one ohmic contact oneach said semiconductor device.

2. The. semiconductor device matrix of claim 1 wherein saidsemiconductor material is germanium.

3. A germanium semiconductor device array comprising a glass member; aplurality of semiconductor devices, each device comprising semiconductormaterial, on a common monocrystalline substrate, within and extendingthrough and supported by said glass member having apertures thereinconforming to said devices, to define semiconductor junctionsrespectively within said apertures, the cross sectional dimension ofeach said aperture intermediate the surfaces of said glass member andsaid substrate being larger than the cross sectional dimension of eachsaid aperture at either the surface of said glass member or saidsubstrate; and at least one electrical current carrying member connectedto each said device and supported by said glass member.

4. A semiconductor device matrix of individual semiconductor devices,each retained in spatial relationship to the other comprising, incombination, a common substrate; a semiconductor-device-retaininginsulating mater-ial having apertures therein; at least twomonocrystalline semiconductor device bodies comprising semiconductormaterial formed in contact with said common substrate to definesemiconductor junctions respectively Within said apertures in a planebetween the surfaces of said device-retaining insulating material; andat least one ohmic contact to each said semiconductor device.

References Cited by the Examiner UNITED STATES PATENTS 2,498,714 2/ 1950Searle 317-234 2,629,802 2/ 1953 Pantchechnikofi 317235 2,680,220 6/1954Starr et al 317-235 2,692,839 10/1954 Christensen et al. 317 -2352,791,731 5/1957 Walker et al 317-234 2,804,581 8/1957 Lichtgarn 3172352,844,770 7/ 1958 Van Vessem 317-234 2,858,489 10/1958 Henkels 317-2352,910,634 10/1959 Rutz 317235 2,982,002 5/ 1961 Shockley 3 17-2343,025,438 3/ 1962 Wegener 317235 JOHN W; I-IUCKERT, Primary Examiner.JAMES D. KALLAM, DAVID J. GALVIN, Examiners.

1. A SEMICONDUCTOR DEVICE MATRIX COMPRISING A MONOCRYSTALLINESEMICONDUCTOR ELEMENT HAVING AT LEAST ONE MAJOR SURFACE; ADEVICE-DEFINING INSULATING MASK IN CONTACT WITH SAID AT LEAST ONE MAJORSURFACE; AT LEAST TWO SEMICONDUCTOR DEVICES COMPRISING SEMICONDUCTORMATERIAL, FORMED WITHIN SAID APERTURES IN SAID DEVICE-DEFINING MASKSPATIALLY SEPARATED ON SAID MAJOR SURFACE, IN CONTACT WITH SAID ELEMENTTO DEFINE SEMICONDUCTOR JUNCTIONS RESPECTIVELY WITHIN SAID APERTURESABOVE THE SURFACE OF SAID ELEMENT; AND AT LEAST ONE OHMIC CONTACT ONEACH SAID SEMICONDUCTOR DEVICE.